zeroRISC
zeroRISC today announced the close of its seed funding round, led by Fontinalis Partners. The investment will accelerate the development of zeroRISC's open hardware security platform for RISC-V embedded systems, expand the engineering team, and deepen partnerships with RISC-V silicon vendors and enterprise customers.
Founded in 2022 in New York by Dominic Rizzo, zeroRISC was built on a straightforward premise: the embedded systems industry needs hardware security infrastructure that is open, auditable, and designed from first principles for the RISC-V era — not adapted from architectures built for a different generation of processors. The company has been working in stealth with select RISC-V chip designers and embedded system manufacturers since its founding, building deep technical relationships while developing its core platform.
Why Now
The timing of this raise reflects a convergence of market forces. RISC-V adoption has accelerated dramatically across the embedded systems market, with an increasing number of commercial SoC designs based on RISC-V cores reaching production. The same period has seen a wave of regulatory attention on embedded security: the EU Cyber Resilience Act, NIST's IoT security guidance, and sector-specific requirements from healthcare and critical infrastructure regulators are all pushing device manufacturers toward more rigorous security architectures.
"Every major hardware security incident of the past decade has involved a system that lacked a credible root of trust," said Dominic Rizzo, CEO and Co-Founder of zeroRISC. "RISC-V gives the industry an opportunity to build that foundation correctly from the start, with an open architecture that can be independently verified. That's what we're building."
What the Funding Enables
The seed funding will be deployed across three priorities:
Platform development: Accelerating the development of the zeroRISC attestation service, the RISC-V SDK, and the key provisioning infrastructure that forms the core of the platform. The next milestone is a production-ready attestation service supporting TCG DICE and IETF RATS, with reference integrations for FreeRTOS and Zephyr.
Team expansion: Growing the engineering team with hardware security specialists, RISC-V firmware engineers, and cryptography researchers. The team is currently hiring in New York and remote. Priority roles include a Principal Hardware Security Architect, a Senior Cryptographic Engineer, and a Developer Relations Engineer focused on the RISC-V ecosystem.
Ecosystem partnerships: Deepening technical integrations with RISC-V silicon vendors, contract manufacturers, and enterprise customers who are deploying RISC-V-based products at scale. zeroRISC will be presenting its attestation architecture at RISC-V Summit later this year and is a member of the RISC-V International security working group.
The Regulatory Tailwind
The seed round comes as hardware security requirements are rapidly moving from best-practice recommendations to regulatory mandates. The EU Cyber Resilience Act, which enters enforcement in 2027, imposes hardware security requirements on connected devices sold in Europe. NIST's IoT security guidance (SP 800-213) and the FCC's IoT labeling program are similarly pushing US-market device manufacturers toward verifiable hardware security architectures.
For RISC-V-based products, this creates an immediate need for the kind of attestable, auditable security infrastructure that zeroRISC is building. Device manufacturers who adopt RISC-V for its cost and customization benefits now need a clear path to hardware security compliance — that is the gap zeroRISC was built to close.
What Customers Are Saying
Early access partners working with the zeroRISC platform pre-announcement have emphasized two themes: the difficulty of implementing hardware root of trust correctly without deep expertise, and the value of an open, auditable architecture for internal security review and external compliance audits.
"Hardware security is not a problem you want to solve from first principles on a project timeline," said one embedded systems architect at an early access partner building industrial IoT hardware on RISC-V. "Having a platform that has already done the hard work — and done it openly so we can verify the claims — is exactly what we needed."
About Fontinalis Partners
Fontinalis Partners is a venture capital firm investing in early-stage deep technology companies at the frontier of hardware, security, and infrastructure software. The firm's thesis centers on foundational technologies with strong network effects in the industries they serve. Cambium's investment in zeroRISC reflects conviction that open, verifiable hardware security infrastructure will become a prerequisite for connected embedded systems across industrial, healthcare, and critical infrastructure markets.
Looking Forward
With the seed round closed, zeroRISC is focused on expanding early customer engagements and reaching platform availability milestones. The company is working with a select group of RISC-V chip designers and embedded system manufacturers on early access programs for the zeroRISC platform. The team will publish its full platform architecture specification publicly in the coming months, inviting community review before the general availability release.
The broader goal is establishing open, verifiable hardware security as the default for new RISC-V designs — not as a premium add-on, but as a baseline expectation baked into the silicon and firmware architecture from day one. The seed funding is the first step in building the infrastructure that makes that possible at scale.
Engineers and architects interested in early access to the platform or in discussing hardware security architecture for their RISC-V projects are invited to contact the team.
