Research

Research & Open Source

We publish hardware security research, RISC-V findings, and open-source security tools. Contributing to the community is core to our mission.

Hardware security researcher in lab

Publications

Technical articles, whitepapers, and findings from the zeroRISC research team.

Apr 1, 2026 8 min
Building a Hardware Root of Trust for RISC-V: A Practical Guide

A step-by-step examination of implementing a silicon-level root of trust on RISC-V platforms.

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Mar 10, 2026 6 min
Why Open Security Architecture Matters for RISC-V Chips

Examining why the RISC-V community benefits from transparent, community-audited security architectures.

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Feb 18, 2026 7 min
Verified Firmware Boot in Embedded Systems: Beyond Secure Boot

Why standard secure boot mechanisms fall short for RISC-V embedded systems.

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Jan 27, 2026 9 min
Threat Modeling for RISC-V: Identifying Silicon-Level Risks

A systematic approach to threat modeling for RISC-V SoCs, from die to application layer.

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Dec 14, 2025 7 min
OpenTitan and the zeroRISC Platform: Complementary Approaches

How the zeroRISC platform complements the OpenTitan open-source silicon root of trust project.

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Nov 20, 2025 6 min
Hardware Security for IoT and Edge Devices: What Architects Need to Know

Practical guidance for hardware architects designing secure IoT and edge devices on RISC-V.

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Oct 15, 2025 8 min
Remote Attestation for RISC-V: Proving Your Hardware Is Who It Says It Is

An overview of remote attestation protocols and their implementation on RISC-V platforms.

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Sep 8, 2025 10 min
Secure Enclaves on RISC-V: Implementation Challenges and Solutions

Deep dive into implementing TEE-style secure enclaves on RISC-V without Arm TrustZone.

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Jul 22, 2025 7 min
Cryptographic Agility in Hardware: Preparing for Post-Quantum

Why hardware security modules need algorithm agility and how to design for post-quantum readiness today.

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Jun 10, 2025 3 min
zeroRISC Closes Seed Round to Advance Open Hardware Security

zeroRISC announces seed funding to accelerate development of its open RISC-V hardware security platform.

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Open Source Projects

We build in public. Our core security primitives, tooling, and reference implementations are available under open-source licenses.

zr-rot-core

Reference implementation of the zeroRISC hardware root of trust. Includes key provisioning, measurement, and attestation primitives in RISC-V assembly and C.

Apache 2.0

zr-attest

Remote attestation library implementing TCG DICE and RATS standards. Supports both hardware-backed and software-based attestation for development environments.

MIT License

zr-verify

Firmware verification toolchain for RISC-V. Integrates with standard build systems to produce cryptographically signed firmware images with embedded measurement chains.

Apache 2.0

Collaborate on Hardware Security Research

We partner with universities, national labs, and chip design teams on joint research. If you are working on RISC-V security, we want to hear from you.

Get in Touch