A complete hardware security stack built natively for RISC-V — from silicon root of trust to verified firmware and remote attestation.
The zeroRISC security stack is composed of layered, independently auditable components. Each layer provides strong guarantees to the layer above it.
Six core security primitives that compose into a complete hardware security solution for RISC-V systems.
Cryptographic identity anchored in silicon. The zeroRISC root of trust cannot be overwritten by software, providing a tamper-resistant foundation for all security guarantees above it.
Cryptographically verified boot chain from ROM through bootloader to application firmware. Every step is measured and attested before the next executes.
Full specification and reference implementation published openly. Your security team can audit every assumption, algorithm, and interface in the platform.
Designed from scratch for the RISC-V ISA, not ported from another architecture. Our security primitives use RISC-V extension points for maximum efficiency and minimal attack surface.
Prove device identity and software state to remote verifiers without trusting the device itself. Standards-compatible attestation for enterprise and cloud integration.
Algorithm-agnostic key management and cryptographic APIs. Upgrade your cryptographic suite without hardware changes — essential for post-quantum readiness.
The zeroRISC SDK supports the full RISC-V ecosystem: LLVM, GCC, OpenOCD, and standard JTAG debug workflows. No proprietary toolchain required.
Our security primitives expose clean C APIs that map naturally onto your existing RTOS or bare-metal firmware architecture. Integration takes hours, not months.
zeroRISC
zr_root_of_trust_t rot;
zr_rot_init(&rot, ZR_ROT_DEFAULT);
zr_attest_token_t token;
zr_attest_generate(&rot, &token);
// token ready for remote verification
We are working with a select group of hardware teams and research institutions. Tell us about your use case and we will be in touch.
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