zeroRISC
When discussing open-source hardware security for RISC-V systems, OpenTitan is inevitably the starting point. As the first open-source silicon root of trust design, OpenTitan represents a meaningful advancement in the field: it demonstrated that a production-quality, auditable security chip design could be developed collaboratively and made freely available.
The zeroRISC platform builds on and extends this foundation. Understanding how the two fit together requires looking at what layer of the security stack each addresses — and where the genuine differences in design philosophy lead to complementary, rather than competing, implementations.
What OpenTitan Is
OpenTitan is an open-source silicon root of trust (RoT) design targeting discrete security chips. It provides a reference implementation of a hardware security chip with a small, auditable RISC-V core (Ibex), cryptographic accelerators, a random number generator, key management logic, and secure storage. The design is intended to be instantiated in silicon by chip manufacturers as a discrete component.
The key design goal of OpenTitan is a fully auditable, community-maintained chip design where the RTL (register-transfer level) code, firmware, test suites, and documentation are all public and subject to external review. This addresses the fundamental problem with proprietary secure elements: you have to trust the vendor's claims because you cannot independently verify them.
Google launched the OpenTitan project in 2019, initially to secure its own infrastructure. The project has since grown into a coalition including dozens of contributing organizations and has attracted serious interest from commercial chip vendors. The Ibex core at the heart of OpenTitan is a 32-bit RISC-V implementation verified for functional correctness and widely used as a security processor in embedded applications beyond OpenTitan itself.
What the zeroRISC Platform Is
The zeroRISC platform operates at a different layer. While OpenTitan defines what a hardware root of trust chip looks like, zeroRISC provides the software infrastructure, integration toolkit, and services that enable a RISC-V application processor to make use of a hardware root of trust — whether that RoT is OpenTitan-based, a proprietary secure element, or an integrated security subsystem.
Specifically, the zeroRISC platform includes:
- Attestation service infrastructure: The server-side components for registering device public keys, receiving attestation quotes, and evaluating them against policy
- SDK for RISC-V firmware: Client-side libraries that handle the cryptographic protocols involved in attestation and verified boot, integrated into the RISC-V toolchain
- Measurement chain tooling: Tools for defining and validating the measurement chain from hardware root to application firmware
- Key provisioning infrastructure: HSM-integrated tooling for manufacturing-time key provisioning that meets regulatory requirements
Think of the zeroRISC platform as the operational layer that connects hardware root of trust capabilities to real-world deployment needs: fleet management, certificate lifecycle, compliance reporting, and firmware update integrity.
Where They Fit Together
An OpenTitan-based chip provides the hardware foundation: the tamper-resistant key storage, the hardware attestation key, the random number generator. The zeroRISC platform provides the operational infrastructure to use that foundation effectively in a deployed system.
A useful analogy: OpenTitan is like a high-quality physical lock. The zeroRISC platform is like the access control system, key management service, and audit logging infrastructure that makes that lock operationally useful at scale.
Engineers working on RISC-V platforms that include an OpenTitan-based RoT can use the zeroRISC platform to implement attestation flows, manage device certificates across their fleet, and establish verified boot chains that extend from the OpenTitan RoT through the application processor firmware.
The interoperability is by design. The zeroRISC attestation SDK supports the OpenTitan DICE attestation flow natively, and our measurement chain tooling has been tested against the OpenTitan reference implementation. Teams that start with OpenTitan hardware can integrate the zeroRISC platform without changes to their RoT silicon design.
Protocol Compatibility
Both projects are committed to the same standards: TCG DICE (Device Identifier Composition Engine) for device identity and attestation certificates, and IETF RATS (Remote ATtestation procedureS) for the attestation protocol. This shared standards base means that attestation evidence generated by an OpenTitan-backed device using the zeroRISC SDK can be verified by any RATS-compatible verifier, not just the zeroRISC attestation service.
This is an important point for enterprise customers evaluating supply chain and vendor lock-in risk: the use of open standards means that the attestation infrastructure is not proprietary to either project. A customer using both OpenTitan hardware and the zeroRISC platform retains the ability to substitute either component with a compatible alternative.
When They Don't Overlap
For RISC-V applications that do not have a discrete OpenTitan-style RoT available — either because of bill-of-materials constraints, power budgets, or form factor — the zeroRISC platform also supports integrated security subsystem architectures where the root of trust functionality is implemented within the main SoC. In these cases, the platform provides the software abstractions and protocols that bridge the integrated security subsystem to the same attestation infrastructure.
OpenTitan is also specifically focused on the silicon design layer. It does not address the provisioning workflows, attestation service infrastructure, or firmware integration tooling that make hardware security operationally useful. These gaps are precisely what the zeroRISC platform addresses, making the two efforts genuinely complementary rather than redundant.
Contributing to Both Ecosystems
The zeroRISC team has contributed improvements back to the OpenTitan project and maintains close coordination with the OpenTitan technical steering committee. We view the growth of the OpenTitan ecosystem as a direct contributor to the kind of verified, auditable hardware security infrastructure that the embedded systems industry needs.
Our open-source contributions include improvements to the OpenTitan test infrastructure, additional coverage for the Ibex core verification suite, and documentation improvements that reduce the barrier for new contributors. We publish all zeroRISC SDK components under Apache 2.0 and MIT licenses, consistent with OpenTitan's licensing approach.
For teams evaluating how OpenTitan and the zeroRISC platform fit into their specific product architecture, we are available for technical consultation.
