A fully documented, community-auditable security architecture for RISC-V — because real security cannot be built on hidden assumptions.
The zeroRISC security model is built on three principles: hardware-enforced isolation, cryptographic measurement of every component, and open specification so any team can audit the design.
We do not ask you to trust our marketing claims. We provide the full threat model, security proofs, and reference implementation for independent verification.
The zeroRISC threat model explicitly addresses the attack classes that matter for embedded RISC-V systems.
Side-channel countermeasures, tamper detection, and memory protection schemes that resist physical access attacks including fault injection and power analysis.
Hardware provisioning and attestation protocols that verify device identity from manufacture through field deployment, closing supply chain compromise vectors.
Cryptographically verified boot chain ensures only signed, measured firmware executes. Rollback protection prevents downgrade attacks to known-vulnerable versions.
Hardware-enforced memory isolation limits the blast radius of software vulnerabilities. Compromised application code cannot access security-critical regions.
Cryptographic keys are stored and used within the hardware security boundary. Even with full software control, an attacker cannot extract raw key material.
Algorithm agility with negotiation safeguards prevents adversaries from forcing weaker cryptographic algorithms. Post-quantum transition is a first-class design goal.
The zeroRISC platform is designed for alignment with major security frameworks and certification programs.
Cryptographic module design follows FIPS 140-3 requirements. Architecture supports Level 2 and Level 3 certification paths for applicable use cases.
Arm Platform Security Architecture (PSA) certification requirements informed the security model design, with Level 2 certification as a target for production deployments.
Designed for industrial control system requirements per IEC 62443, including Security Level 2 and 3 profiles for critical infrastructure applications.
Hardware root of trust architecture implements NIST SP 800-193 guidelines for platform firmware resiliency, including protection, detection, and recovery.
Device identity and attestation follows Trusted Computing Group DICE (Device Identifier Composition Engine) architecture for interoperable device attestation.
Security architecture is structured to support Common Criteria evaluation, with EAL4+ as the target assurance level for enterprise and government deployments.
Our team is available to walk through the threat model, discuss certification requirements, or review your specific deployment scenario.
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