Founded in 2022 in New York, zeroRISC is on a mission to make silicon-level security accessible to every RISC-V hardware team.
RISC-V represents a historic shift in semiconductor design — an open instruction set that lets any team build processors without licensing fees or proprietary lock-in. But openness at the ISA level does not automatically produce secure systems. Hardware security requires deliberate, expert engineering.
zeroRISC was founded to solve this gap. Our team comes from silicon security, RISC-V implementation, and cryptographic engineering backgrounds. We build the security primitives that RISC-V chip designers need — and we build them openly, so the entire ecosystem benefits.
Seed-backed and based in New York, we work with chip design teams, embedded systems companies, and critical infrastructure operators who cannot afford to get hardware security wrong.
Experienced engineers with deep roots in silicon security, RISC-V architecture, and cryptographic systems.
Our seed round is led by investors who understand the long cycles and high stakes of semiconductor security.
Investor names listed for representation purposes only.
We are looking for hardware security engineers, RISC-V specialists, and cryptographic systems researchers to join the team.
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zeroRISC