We publish hardware security research, RISC-V findings, and open-source security tools. Contributing to the community is core to our mission.
Technical articles, whitepapers, and findings from the zeroRISC research team.
A step-by-step examination of implementing a silicon-level root of trust on RISC-V platforms.
Read MoreExamining why the RISC-V community benefits from transparent, community-audited security architectures.
Read MoreWhy standard secure boot mechanisms fall short for RISC-V embedded systems.
Read MoreA systematic approach to threat modeling for RISC-V SoCs, from die to application layer.
Read MoreHow the zeroRISC platform complements the OpenTitan open-source silicon root of trust project.
Read MorePractical guidance for hardware architects designing secure IoT and edge devices on RISC-V.
Read MoreAn overview of remote attestation protocols and their implementation on RISC-V platforms.
Read MoreDeep dive into implementing TEE-style secure enclaves on RISC-V without Arm TrustZone.
Read MoreWhy hardware security modules need algorithm agility and how to design for post-quantum readiness today.
Read MorezeroRISC announces seed funding to accelerate development of its open RISC-V hardware security platform.
Read MoreWe build in public. Our core security primitives, tooling, and reference implementations are available under open-source licenses.
Reference implementation of the zeroRISC hardware root of trust. Includes key provisioning, measurement, and attestation primitives in RISC-V assembly and C.
Apache 2.0Remote attestation library implementing TCG DICE and RATS standards. Supports both hardware-backed and software-based attestation for development environments.
MIT LicenseFirmware verification toolchain for RISC-V. Integrates with standard build systems to produce cryptographically signed firmware images with embedded measurement chains.
Apache 2.0We partner with universities, national labs, and chip design teams on joint research. If you are working on RISC-V security, we want to hear from you.
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