Engineering-first, certification-proven
The zeroRISC team combines hardware security research, RTL design, FIPS validation, and silicon application engineering — the full stack required to deliver certified root-of-trust IP that actually integrates into production tape-outs.
Silicon security architecture and OpenTitan project background. Co-founded zeroRISC in Cambridge, MA in 2022 to commercialize FIPS 140-3 Level 3-validated OpenTitan IP. Leads company strategy and IP licensing.
10+ years in synthesizable RTL design for cryptographic and security IP. Leads microarchitecture, foundry node characterization, and timing closure for the zeroRISC RoT core.
Specializes in DV methodology for security IP, physical attack countermeasure verification, and FIPS 140-3 validation evidence package preparation. Leads the assurance case for Level 3 certification.
Customer-facing integration support: OTP provisioning workflows, SoC bus integration debugging, and tapeout checklist reviews. Primary engineering contact for OEM license customers.
Work at zeroRISC?
We're building the team at the intersection of hardware security research and commercial silicon IP. Reach out if you're interested in joining.