Open-source silicon security, commercially hardened.
Founded 2022 in Cambridge, MA. zeroRISC makes FIPS 140-3 Level 3-validated root-of-trust IP accessible to OEM tape-out teams — eliminating the multi-year design validation bottleneck without replacing your product certification process.
Make FIPS-validated root-of-trust IP accessible to every OEM tape-out
Bringing a silicon design through FIPS 140-3 Level 3 certification is a multi-year, multi-million dollar project. The audit process alone — before any engineering work — takes 12–18 months. For most OEM tape-out teams, this means either shipping uncertified security or delaying products by two years.
zeroRISC addresses this bottleneck. We carry the OpenTitan root-of-trust foundation through FIPS 140-3 Level 3 design validation once, and ship the result as licensable RTL. OEM teams integrate the pre-validated block; the 18–24 month audit runway on the cryptographic module itself is already behind them. Note: CMVP product submission for your SoC remains your team's process — we don't certify on your behalf.
The open-source OpenTitan specification is the technical foundation — it's the most rigorously peer-reviewed root-of-trust architecture available. zeroRISC is the commercial hardening and validation layer that makes it tape-out ready for production silicon.
Dominic Rizzo
CEO & Co-Founder, zeroRISCDominic Rizzo spent years in hardware security research and open-source silicon architecture before co-founding zeroRISC in Cambridge, MA in 2022. His background includes silicon security architecture, FIPS 140-3 validation methodology, and direct involvement in the technical development and governance of the OpenTitan root-of-trust project.
The founding insight was direct: the OpenTitan specification is technically the most rigorously peer-reviewed open root-of-trust architecture available — but OEM adoption stalls because carrying it through FIPS 140-3 Level 3 design validation is a multi-year undertaking that no individual tape-out team can absorb. The solution is to do it once, at the IP level, and ship the result as licensable RTL. That is what zeroRISC does.
Engineering-first, certification-proven
Silicon security architecture and OpenTitan project background. Co-founded zeroRISC in 2022. Leads IP licensing and FIPS 140-3 validation strategy.
Synthesizable RTL design and foundry node qualification. Leads microarchitecture and timing closure.
FIPS validation, DV methodology, and physical attack countermeasure verification. Leads security assurance.
Customer integration support, OTP provisioning workflows, and tapeout checklist reviews.
Talk to the team
Contact us to discuss your tape-out timeline, foundry node, or FIPS scope requirements.