Team

Hardware Security Veterans

The zeroRISC team brings decades of combined experience in silicon design, hardware security architecture, and open-source RISC-V development.

Meet the Team

Founded by engineers who have built production security systems at chip vendors, cloud providers, and open-source hardware projects.

Dominic Rizzo

Dominic Rizzo

CEO & Co-Founder

Dominic has spent his career at the intersection of open-source silicon and hardware security. Prior to founding zeroRISC, he led security architecture for RISC-V platforms and contributed to the OpenTitan root of trust project. He holds a degree in Electrical Engineering and Computer Science.

Daniel Wei

Daniel Wei

VP of Hardware Security

Daniel brings deep expertise in silicon-level security design, having previously worked on hardware security modules and secure enclave implementations at a leading semiconductor company. He specializes in threat modeling for embedded systems and cryptographic hardware acceleration on RISC-V.

Amara Johnson

Amara Johnson

Lead RISC-V Architect

Amara is a core contributor to the RISC-V International standards working groups and has designed security extensions for multiple production RISC-V cores. Her work on physical unclonable functions and hardware attestation forms the technical foundation of the zeroRISC platform.

Our Expertise

The capabilities that power the zeroRISC platform.

Silicon Design

RTL design, FPGA prototyping, and tape-out experience for security-critical hardware blocks. Our team has taken security IP from specification to silicon.

Cryptographic Engineering

Hardware-accelerated symmetric and asymmetric cryptography, key management, and post-quantum readiness for RISC-V embedded platforms.

Threat Modeling

Systematic threat analysis for hardware systems, including side-channel attacks, fault injection, supply-chain risks, and firmware compromise scenarios.

Open Source Development

Active contributors to RISC-V International, OpenTitan, and Zephyr RTOS security subsystems. We build in the open because we believe open development produces better security.

Attestation & Identity

Remote attestation protocol design, device identity provisioning, and certificate authority infrastructure for large-scale embedded deployments.

Security Research

Published research on RISC-V security extensions, hardware root of trust design, and verified firmware boot chains. We advance the field, not just our product.

We’re Growing

zeroRISC is looking for engineers who care about hardware security, open-source development, and the RISC-V ecosystem. If that’s you, we want to talk.

Get in Touch