Product — zeroRISC Hardware Security

Core Product Components

Every zeroRISC product is designed as a composable security primitive. Start with root of trust, layer verified boot, extend with attestation.

Hardware Root of Trust

The foundation of the zeroRISC security stack. A silicon-anchored cryptographic identity that cannot be overwritten by software, firmware, or supply-chain attacks. Every downstream security guarantee derives from this core primitive.

Technical details

Verified Firmware Boot

Cryptographically verify every firmware image before execution. zeroRISC's verified boot chain ensures that only signed, unmodified firmware can run on your RISC-V system — from first instruction to application startup.

Security model

Remote Attestation

Prove the integrity of a remote device to any verifier without physical access. zeroRISC's attestation service enables fleets of embedded devices to report their security state in real time, supporting zero-trust architectures at scale.

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Cryptographic Key Management

Hardware-isolated key storage and derivation using RISC-V physical unclonable functions (PUFs) and secure key hierarchies. Keys are provisioned at manufacture and never exposed in plaintext, even during firmware updates.

Security details

RISC-V Security SDK

A developer-friendly SDK that exposes zeroRISC security primitives through a clean, well-documented API. Compatible with standard RISC-V toolchains including GCC, LLVM, and Zephyr RTOS, with example integrations for common embedded frameworks.

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Fleet Management Console

Monitor and manage the security posture of your entire RISC-V device fleet from a single dashboard. Track attestation status, firmware versions, key rotation schedules, and security events across thousands of deployed devices.

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RISC-V Native

Built for the RISC-V Ecosystem

Unlike security solutions retrofitted from ARM or x86, every zeroRISC product is designed from the ground up for RISC-V architecture. We leverage RISC-V's open ISA extensibility to implement security features that would be impossible on proprietary architectures.

Compatible with RV32 and RV64 cores
Works with SiFive, OpenHW Group, and custom cores
RISC-V International member and contributor
Supports Zephyr, FreeRTOS, and bare-metal targets

// zeroRISC SDK integration example
#include "zerorisc/rot.h"
 
int main(void) {
  zr_rot_t rot;
  zr_rot_init(&rot, ZR_ROT_FLAGS_DEFAULT);
 
  // Verify firmware before boot
  if (!zr_verify_firmware(&rot, fw_image)) {
    zr_halt_secure();
  }
 
  // Attest device state
  zr_attest_report_t rpt;
  zr_attest_generate(&rot, &rpt);
  return 0;
}

Deployment Models

zeroRISC products fit into your existing hardware design flow. Choose the integration path that works for your architecture.

Silicon IP

Integrate the zeroRISC root of trust as RTL IP into your custom RISC-V SoC. Full control, full auditability, zero added complexity to your security model.

Software Stack

Deploy the zeroRISC firmware security stack on existing RISC-V hardware. Verified boot and attestation without requiring custom silicon.

Managed Security

Full-stack deployment with zeroRISC operating the attestation infrastructure. Ideal for teams who need production-grade security without in-house HSM expertise.

zeroRISC Security Products