OpenTitan-Based Silicon Root-of-Trust IP
Designed against FIPS 140-3 Level 3. Synthesizable RTL. Full DICE attestation chain, OTP-backed lifecycle controller, and physical attack countermeasures — licensable, tape-out ready.
Request DatasheetBlock hierarchy and attestation chain
The zeroRISC RoT IP Core is structured around eight functional sub-blocks sharing an internal AHB-Lite bus. The DICE Attestation Engine orchestrates certificate chain generation at power-on, using secrets held in the OTP Controller and processed by the Key Manager.
IP specifications and interfaces
| Feature | Specification | Notes |
|---|---|---|
| Symmetric Cipher | AES-256-GCM | NIST FIPS 197 / SP 800-38D |
| Hash Function | SHA-3-256 / SHA-2-256 | NIST FIPS 202 / 180-4 |
| Asymmetric | ECDSA-P384 | NIST FIPS 186-5; used for attestation signing |
| RNG | CSRNG (NIST SP 800-90A) | CTR_DRBG with TRNG seed input |
| Bus Interface | AHB-Lite / AXI4-Lite | 32-bit, little-endian; selectable at integration |
| Foundry Nodes | TSMC 28nm HPM, GF 22FDX, SMIC 40nm | Additional nodes available via NDA |
| Gate Count | ~350–420 kGE (estimated) | Configuration-dependent; DFT overhead separate |
| Supply Voltage | 0.8 V – 1.1 V | Node-dependent; IO ring separate |
| Attestation Protocol | DICE / DMTF DSP0267 | UDS, CDI_0, CDI_1, application cert chain |
| Lifecycle States | DEV / PROD / LOCKED / RMA / EOL | OTP-backed, HMAC-authenticated transitions |
Designed against FIPS 140-3 Level 3
FIPS 140-3 Level 3 requires physical security mechanisms beyond logical security — tamper-evidence, tamper-response, and identity-based operator authentication. The zeroRISC IP is designed against all Level 3 requirements: the architecture, physical security posture, and cryptographic algorithm selection are built to that target from first principles.
The license package includes FIPS 140-3 design validation documentation covering the security policy, physical security mechanisms, and cryptographic algorithm validation records. CMVP product module submission for your end device remains your team's process — zeroRISC does not file CMVP on your behalf.
Deep-dive into each IP component
Attestation Engine
DICE-compliant certificate chain engine. UDS derivation, CDI_0/CDI_1, boot-stage attestation certificates. Register map and API surface documented.
Lifecycle Controller
OTP-backed state machine spanning DEV, PROD, LOCKED, RMA, EOL. HMAC-authenticated transition commands. Tamper-evident state persistence.
Fault-Injection Countermeasures
EMFI, laser fault, voltage glitch, and power side-channel countermeasures. Redundant logic paths, alert architecture, PRNG pipeline randomization.
Request the IP Core datasheet
Full specification PDF, FIPS 140-3 design validation documentation overview, and integration package contents — delivered after NDA.