TAPE-OUT INTEGRATION
RTL delivery to tapeout — the integration path
The zeroRISC IP integration package is designed to fit into an existing SoC design flow without requiring restructuring of the surrounding architecture. Bus integration, OTP provisioning, and tapeout signoff — in 8–10 weeks.
Read Integration GuideINTEGRATION TIMELINE
Week 1
RTL Delivery
Wks 2–3
Bus Integration
Wks 4–6
DV Closure
Wks 7–10
Tapeout Sign-off
SoC INTEGRATION DIAGRAM
Root-of-trust placement in SoC context
DELIVERY PACKAGE
What arrives with the RTL delivery
RTL SourceSynthesizable Verilog/SystemVerilog source, fully commented
Timing ConstraintsSDC constraints per foundry node (TSMC 28nm, GF 22FDX, SMIC 40nm)
Synthesis ScriptsReference synthesis flow (Synopsys DC / Cadence Genus compatible)
DFT Hook AnnotationsScan insertion boundary documentation and test mode port assignments
DV TestbenchUVM testbench infrastructure for attestation API and lifecycle transitions
Integration Guide PDFStep-by-step bus connection, OTP map, power domain, and tapeout checklist
LEF/GDS AbstractPre-validated abstract views for tapeout DRC/LVS signoff (per foundry node)
FIPS 140-3 Design Validation PackageSecurity policy document, cryptographic algorithm validation records, and Level 3 physical security evidence — supports your team's CMVP product submission
FOUNDRY SUPPORT
Validated foundry nodes
| Foundry / Node | PDK Version | Validation Status | Notes |
|---|---|---|---|
| TSMC 28nm HPM | 28HPM N-1 | Validated | Reference node for FIPS certification scope |
| GlobalFoundries 22FDX | 22FDX EV | Validated | FD-SOI; low-power IoT / automotive segment |
| SMIC 40nm | 40LP | Validated | Cost-optimized consumer and industrial segment |
| Other nodes | — | Available via NDA | Contact engineering for node-specific characterization |
INTEGRATION TIMELINE
8–10 week integration path
Week 1
RTL Delivery
Secure file delivery of RTL source, synthesis constraints, and integration guide. NDA signed, license agreement executed. Engineering kickoff call with zeroRISC application engineer.
Weeks 2–3
Bus Integration
Connect attestation engine and lifecycle controller to SoC interconnect via AHB/AXI4-Lite bridge. Apply reference tie-off scripts. Connect alert bus to SoC alert handler.
Weeks 4–6
DV Closure
Run provided UVM testbench. Configure OTP memory map for target lifecycle states. Provisioning test vectors validated. Functional coverage target reached.
Weeks 7–10
Tapeout Sign-off
Run DRC/LVS using pre-validated LEF/GDS abstract views. zeroRISC application engineer reviews completed tapeout checklist. Sign-off documentation provided for fab submission.
Contact our integration engineering team
Discuss your SoC architecture, foundry node, and integration timeline directly with zeroRISC application engineers. The zeroRISC IP is a hardware root-of-trust IP block — it does not replace your existing secure-boot toolchain, key provisioning infrastructure, or product-level CMVP submission process.