Industry insights, product thinking, and commentary on the future of silicon security from the zeroRISC team.
The EU CRA enters enforcement in 2027 — and it changes the compliance calculus for every hardware manufacturer selling into Europe. Here is what RISC-V teams need to understand now.
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Proprietary security architectures in embedded hardware are not just philosophically wrong — they are operationally fragile. A look at the evidence and the alternative.
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Software supply chain security gets all the attention. But the most dangerous attacks start before the first line of firmware is ever written. Why silicon-level attestation changes the equation.
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Zero trust requires verifiable device identity. For embedded systems, that identity must be hardware-anchored. Here is what a credible zero-trust architecture for RISC-V device fleets looks like.
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NIST finalized its post-quantum standards in 2024. For hardware teams, the decisions made today about cryptographic agility will determine whether the migration is manageable or catastrophic.
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Hardware security due diligence has matured. Here is what sophisticated investors are asking hardware founders, and how to answer credibly.
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For security-sensitive applications, how does RISC-V stack up against ARM? An honest technical assessment of where each architecture leads, lags, and offers structural advantages.
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OpenTitan is the first open-source silicon root of trust. Here is what it is, how it works, and why zeroRISC builds on its foundation for RISC-V hardware security.
Read MoreOur Research Lab publishes peer-reviewed articles on RISC-V security architecture, root of trust implementation, and verified firmware design.
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