zeroRISC was founded in 2022 with a single conviction: the open RISC-V architecture deserves a security foundation that is equally open, auditable, and uncompromising.
RISC-V is reshaping the semiconductor landscape. Thousands of chip designers, embedded engineers, and infrastructure operators are building on an open instruction set for the first time. But open hardware deserves open security — and the industry has not had that until now.
zeroRISC builds the security primitives that the RISC-V ecosystem needs: a hardware root of trust you can audit, a verified boot chain you can inspect, and an attestation framework your team can reason about. No black boxes. No security through obscurity.
Our work is grounded in the OpenTitan project and years of hardware security research. We believe the best security is the kind that stands up to public scrutiny — and we build accordingly.
The story behind zeroRISC begins at the intersection of open-source silicon and enterprise security.
By 2022, RISC-V had crossed a threshold. Major silicon vendors, cloud providers, and government agencies were committing to RISC-V as a strategic architecture. The ecosystem was real — but the security tooling was not.
Our founding team contributed to Google's OpenTitan project — the first open-source silicon root of trust. We saw firsthand what was possible when hardware security was designed in the open, and we set out to bring that to RISC-V natively.
Critical infrastructure operators, IoT platform companies, and edge computing vendors all needed RISC-V security that met enterprise requirements: auditable, certifiable, and supported. zeroRISC closes that gap.
zeroRISC is seed-funded by investors who understand deep-tech hardware security.
Fontinalis Partners invests in early-stage deep technology companies at the frontier of hardware, security, and infrastructure software. Their backing reflects conviction that open, verifiable hardware security will define the next generation of connected embedded systems.
Whether you are a chip designer, embedded security engineer, or infrastructure operator — we want to hear from you. Let’s build the security foundation the RISC-V era deserves.
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